In the testing procedure for print circuit board assembly (PCBA), an important step in the front-end process is detecting whether the pins on integrated circuits (ICs), connectors and other electronic devices are properly connected to the printed circuit board. Such testing not only can increase product quality, it can also detect manufacturing defects in the front-end processes. Today, the “automatic optical inspection” method (AOI) has replaced the conventional manual inspections. The AOI method not only reduces cost and eliminates human errors, it also increases the speed of inspection. The “In Circuit Test” (ICT) provides another testing method. Under ICT, though it is required to fit different fixtures for different device under testing (DUT), the probes on the fixture are capable of detecting all the ICs on the printed circuit board assembly. Moreover, the fast testing speed, the accuracy of locating the defects, and a testing coverage rate higher than both automatic optical inspection and automatic X-ray inspection, are all noted advantages of ICT.
The Boundary-scan testing is also known as JTAG testing or IEEE1149.1. Such technique was proposed to IEEE committee by Join Testing Action Group (JTAG) in 1988, and the standard for “Standard Testing Access Port and Boundary-Scan Architecture” (IEEE std. 1149.1-1900) was established in 1990.
Referring to FIG. 1A, it shows a schematic of a conventional testing structure of the Boundary-scan testing. The testing structure comprises a printed circuit board 102, a socket 104, a chipset 106, and a contact object 108. The socket 104 is fixed on the printed circuit board 102 by welding method for communicating with the printed circuit board 102. The chipset 106 is disposed over the socket 104 and electrically connected to the socket 104 for transmitting signal.
In the testing process, the IC with boundary-scan testing function (not shown) receives a testing data from the testing signal source and shifts the testing data to the boundary scan cells by serial inputting method. The testing data can then be serially transferred from the testing data output pin of the IC with boundary-scan testing function to the testing data input pin of the chipset 106, following a data shifting test in the boundary scan cells. The shifted data can be observed at the testing data output pin of the chipset 106.
In FIG. 1A, the chipset 106 is not pressed by the fixing element (not shown). Therefore, while the chipset 106 is pressed by the contact object 108, the chipset 106 can be electrically contacted to the socket 104. If the force pressed by the contact object 108 is sufficient, then the test result can match real life situation. In the testing structure, the back plate is not fixed to another surface of the printed circuit board 102 so that the testing data is transmitted to the printed circuit board 102. In the same way, a sensing signal can be detected on another surface of the printed circuit board 102. In FIG. 1A, the testing structure is used for detecting the connection between the printed circuit board 102 and the socket 104.
Referring to FIG. 1B, it shows another schematic of a conventional testing structure of the Boundary-scan testing. The testing structure comprises a printed circuit board 102, a socket 104, a back plate 110, and a fixing element 112. The chipset 106 is plugged in the socket 104 and fixed by the fixing element 112. The testing method of FIG. 1B and FIG. 1A are the same and not explained here.
In the structure of the FIG. 1B, the back plate 110 is used for supporting the printed circuit board 102 against a force pressed by the fixing element 112. However, a testing point can not be tested by a probe due to the fact that the testing point is disposed in an area covered by the back plate 110. The testing point may be limited by the back plate 110 when the back plate 110 has been fixed to another surface of the printed circuit board 102. Therefore, the test data can not be obtained in the testing process.
In FIGS. 1A and 1B, the chipset 106 can be an actual central processing unit (CPU) or a Socket Test Technology (STT). The Socket Test Technology is manufactured by Intel Corporation. The size and the outward appearance of the Socket Test Technology are the same as those of the actual central processing unit. The difference between the actual central processing unit and the Socket Test Technology is the inner circuit.
In FIG. 1B, the testing structure is used for detecting the connection between the printed circuit board 102 and the socket 104, and the contact between the chipset 106 and the grids of the socket 104.
FIG. 1C shows another schematic of a conventional testing structure. The testing structure 100c comprises a printed circuit board 102, a socket 104, a vectorless testing plate 114, an operation amplifier 115 and a probe 116. A testing data is transmitted to the socket 104 through the printed circuit board 102. The vectorless testing plate 114 is disposed over the socket 104 and electrically connected to operation amplifier 115. The operation amplifier 115 is electrically connected to the probe 116 for amplifying a sensing signal. The vectorless testing plate 114 is electrically coupled to the socket 104. The probe 116 is electrically connected to a signal processing unit (not shown).
The difference between FIG. 1C and FIG. 1A is that a sensing signal in 1C is generated by the vectorless testing plate 114 due to the electrically coupling between the vectorless testing plate 114 and the socket 104. The sensing signal is amplified by the operation amplifier 115 and outputted to the probe 116. The probe 116 transmits the sensing signal to the signal processing unit. A capacitance value can then be calculated by the sequential signal processing unit. Such a Capacitive Coupling Testing was first disclosed by Agilent Technologies in U.S. Pat. No. 5,254,953 in 1993, and it is now broadly adopted by the industry.
In FIG. 1C, the testing structure is used for detecting the connection between the printed circuit board 102 and the socket 104. However, after the step of reflow, the testing step has to rework if the fixing element and the back plate are fixed on the printed circuit board 102. And the fixing element and the back plate need to be removed while the testing step is reworked.
FIG. 2 shows a block diagram of a conventional testing system. In the conventional technology, the testing system 200 comprises a testing signal source 210, a signal sensing unit 230, a signal processing unit 250, a analysis unit 270, and an IC with boundary-scan testing function 290. The testing system is used for sensing whether the pins of the chipset 106 are properly connected to the printed circuit board 102.
Please refer to FIG. 2, the testing signal is outputted to the IC with boundary-scan testing function 290 by channel selector 280. The channel selector 280 will select a proper channel to deliver the signal, and the IC with boundary-scan testing function 290 will deliver the testing signal to the chipset 106 through the printed circuit board 102. The signal sensing unit 230 will then detect the sensing signal that corresponds to the testing signal.
The signal sensing unit 230 comprises a TestJet probe and a multiplex card to deliver the sensing signals to the signal processing unit 250. An analog signal amplifier 260 and a filter 262 are respectively disposed in the signal processing unit 250 for receiving the sensing signal and filtering the noise of the sensing signal. The analysis unit 270 will analyze the digital sensing signals. By determining whether the sensing signals fall within a range of predetermined reference values, the state of electrical connections of the pins can be determined.
In the conventional testing system 200, an operation amplifier is disposed on the sensor plate. The probe is in contact with the sensor plate. The capacitance value is inversely proportional to the distance between the sensor plate and the chipset 106. Since Chipset 106 can be a socket, connector, or integrated circuit, the capacitance value can not be easily determined. Moreover, the capacitance value may not be properly determined due to the fact that sensor plate and the chipset are not parallel.
As a result, it is necessary to introduce a new technique to address all the insufficiencies of the prior art. A testing system and method that overcome the obstacles of signal delivery is required to increase the coverage of inspection and to eliminate examination blind spots.